1. Field of the Invention
The present invention relates to memory devices, and more particularly to a differential non-volatile memory device and a bit reading method for such a memory device.
2. Description of Related Art
Conventional differential non-volatile memory devices have memory cells of the OTP (One Time Programmable) type (i.e., memory cells that are programmed only once and which do not lose the stored information when the memory device is no longer supplied with power).
Such a memory device is shown in FIG. 1. The device comprises two memory blocks 100 and 200 having memory cells 1 and 2, which are formed by respective capacitors C1 and C2, and driving MOS transistors M1 and M2. Each of the capacitors C1 and C2 is connected between a supply voltage HV having a high value and the drain terminal of one of the driving transistors M1 and M2, which has its source terminal connected with a reference voltage, which is generally ground. During the programming of the memory cells 1 and 2, one of the two capacitors C1 and C2 is altered. That is, a high potential difference is applied at its terminals, until it assumes the properties of a resistor (known as “antifuse” programming). In the programming, the supply voltage HV is typically about 14V and, in the case in which the capacitor C1 has to be altered, the MOS transistor M1 is turned on so that a potential difference of about 14V is applied at the terminals of the capacitor C1; the MOS transistor M2 in such a case is turned off.
It is alternatively possible to program the memory cells of a differential non-volatile memory device by using a “fuse” approach. In such a case, two resistances are put in the place of the two capacitors C1 and C2, and one of the resistances is altered by a high potential difference at its terminals so as to obtain a capacitor.
A memory device provided with two memory cells with one having a capacitive behavior (e.g., the memory cell 2 of the device of FIG. 1) and the other having a resistive behavior (e.g., the memory cell 1 of the device of FIG. 1) stores only one bit and its complementary bit. At the end of the programming, both the driving transistors M1 and M2 are turned off.
During reading, a reading circuit 3 is activated by a control signal READ that simultaneously turns on transistors M3 and M4, which are connected respectively with the drain terminals of the transistors M1 and M2 at the circuit points C and D, respectively. The supply voltage HV assumes a low voltage value typically of about 5V during the reading.
Successively, a pre-charge step occurs in which the transistors M5 and M6, which have their source terminals connected with the respective source terminals of the transistors M1 and M2 (in this case that means connected to ground), and their drain terminals connected with the source terminals of the transistors M3 and M4, are turned on by a control signal P applied at their gate terminal. In such a way, a path is formed between the supply HV and ground. In the memory device of FIG. 1, the circuit points A and B can be distinguished as follows. The circuit point A is formed by the source terminal of the transistor M3, the drain terminal of the transistor M5, the input terminal of a buffer B1, and one of two input terminals of a device 4 that has a high impedance at its input terminals and that is turned off during the pre-charge step. The circuit point B is formed by the source terminal of the transistor M4, the drain terminal of the transistor M6, the input terminal of a buffer B2, and the other input terminal of the device 4. The pre-charging causes the circuit points A and B to assume equal voltages (in this case the ground voltage, and in general the lowest voltage applied to the memory device).
At the end of the pre-charge step, the transistors M5 and M6 are turned off while the transistors M3 and M4 are turned on. This causes the circuit points A and B to become high impedance points and have different behaviors. Since the capacitor C1 has resistive properties, the voltage at the circuit point A will assume a value substantially equal to the supply voltage HV, while the voltage at the circuit point B is constant with a value substantially equal to ground.
After a time period necessary for the circuit points A and B to assume different voltage values, the device 4 is activated. The device is a discriminator which amplifies the voltage difference between the circuit points A and B.
At the end, the bit 1 and its complementary bit, the bit 0, are obtained at the output terminals Out1 and Out2 of the inverting buffers B1 and B2. In accordance with the selected convention, the bit 1 or its complementary bit can be linked to the memory cell 1 having resistive behavior.
In such a memory device, in the pre-charge step a resistive path between supply and ground occurs which causes a considerable power loss that is limited only by the on resistances of the transistors M3 and M4 and by the resistive value of the memory cell 1 having resistive behavior.
A solution to this drawback can be to put into the memory device of FIG. 1 two further resistances for limiting the power loss. These resistances can be connected, for example, with the drain terminals of the transistors M3 and M4 and the circuit points C and D in FIG. 1.
Nevertheless, the use of these additional resistances increases the bit reading time and also increases the area occupied in the memory device chip. In the case in which there are a great number of bits, this increase in the occupied area becomes considerable.